1. Field of the Invention
The present invention relates to a dynamic semiconductor memory which requires periodic refreshing to preserve data, and a refresh control method thereof.
2. Description of the Related Art
Dynamic memory that can be integrated on a logic chip (SoC memory: System-On-a-Chip memory) has been finding widespread use in recent years. Compared with a discrete (single) memory, the SoC memory can achieve higher data transfer rates because the data input/output bit width can be increased. It also offers the advantage of reducing the system current consumption, since the wiring load for logic-to-memory connection is greatly reduced.
More specifically, when, for example, a discrete dynamic semiconductor memory (DRAM) is used such as a memory used in a personal computer, access speed is slow and power consumption increases, but when a DRAM is embedded into a SoC, not only can the access speed be increased and the power consumption reduced, but also the size can be reduced and performance increased.
However, in the case of the SoC memory, compared with a discrete dynamic semiconductor memory, it is difficult to increase the size of a capacitor for holding data, and also, the cell leakage current is relatively large; for these and other reasons, the memory cell data retention time (tREF) of the SoC memory is generally short.
Here, when the total bit count of the dynamic semiconductor memory is denoted by T, and the number of bits accessed in one refresh (data retention) operation by R, then the refresh operation must be performed T/R times within the tREF time. This means that the number of refresh operations per unit time must be increased as tREF becomes shorter.
In the prior art SoC memory, this issue has been addressed, for example, by reducing T (the total bit count) or by increasing R (the number of bits accessed in one refresh operation) as much as possible compared with a discrete memory, and the reduced tREF time has not been much of a problem. Further, the problem has also been solved by performing the usual memory access and the refresh access in a time-division fashion and by not requesting an external refresh command.
In the prior art, Japanese Unexamined Patent Publication (Kokai) No. 2003-173676 discloses a semiconductor storage device in which, when contention occurs between a refresh operation and an external access request for the same data, the external access is accomplished in a time apparently equal to one memory core operation; to achieve this, multiple bits of data having the same address are distributed across a plurality of memory cell blocks, and the refresh operations of the plurality of memory cell blocks are controlled independently of each other so that the refresh operations of a first memory cell block and a second memory cell block are performed with different timings.
Further, in the prior art, Japanese Unexamined Patent Publication (Kokai) No. 2000-163956 discloses a semiconductor storage device that allows an access operation and a refresh operation to be performed simultaneously to the same bank; in this device, a plurality of bit line groups are respectively connected to a plurality of first sense line groups via first switch means and also to a plurality of second sense line groups via second switch means, and the first and second switch means are controlled independently of each other to enable data to be read out of memory cells simultaneously selected by a certain activated word line, while at the same time, refreshing data in memory cells simultaneously selected by another activated word line.
The prior art and its associated problems will be described later with reference to the accompanying drawings.